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ltc1840 1 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. the ltc ? 1840 is a fan controller with two 8-bit current output dacs, two tachometer interfaces, and four general purpose i/o (gpio) pins. it operates from a single supply with a range of 2.7v to 5.75v. a current output dac is used to control an external switching regulator, which controls the fan speed. a current output dac and tachometer allow a controller to form a closed control loop on fan velocity. the gpio pins can be used as digital inputs or open drain pull-down outputs. the part features a simple 2-wire i 2 c and smbus compat- ible serial interface that allows communication between many devices. the interface includes a fault status register that reflects the state of the part and which can be polled to find the cause of a fault condition. other operational characteristics of the part, such as dac output currents, gpio modes, and tachometer frequency, are also pro- grammed through the serial interface. two address pins provide nine possible device addresses. the blast pin is provided to force the dac output currents to program the maximum regulator output voltages through a single pin and gate the operation of the serial access timer. n servers n desktop computers n power supplies n cooling systems n two 8-bit current dacs n dacs guaranteed monotonic n known ic state on power-up n serial interface access timer with disable n 2-wire serial interface compatible with i 2 c tm and smbus n 2 programmable fan tachometer interfaces n 4 programmable general purpose i/os n small 16-pin ssop package n single 2.7v to 5.75v supply operation n fault output signal n status register n fan blasting function n nine addresses using two programming lines applicatio s u features descriptio u typical applicatio u final electrical specifications dual fan controller with 2-wire interface june 2001 1840 ta01 run/ss i th v fb gnd v in sense pgate mode ltc1771 + c fb1 100pf c c1 220pf r sense1 0.05 r sense2 0.05 4 3 2 1 r fb1a 75k r fb1b 28k c out1 150 f + dc fan c vin1 22 f l1 47 h si6447dq ups5817 tach out 3.3v 3.3v 3.3v 3.3v 3.3v run/ss i th v fb gnd v in gnd v cc sense pgate mode ltc1771 + c fb2 100pf c c2 220pf 4 3 2 1 r fb2a 75k r fb2b 28k c out2 150 f + dc fan c vin2 22 f l2 47 h si6447dq ups5817 tach out 3.3v 12v 12v system reset gpi04 blast idacouta gpi03 idacoutb tachb tacha fault sda scl a0 a1 gpi01 gpi02 ltc1840 r c1 10k r c2 10k to master nc nc 130 led1 130 led2 address = 1110010 (8 others possible) 2-nmb 6820pl-04w-b29-d50 fans 1.1a nom at 12v 10k 10k 10k + 10 f 0.1 f low parts count, high efficiency dual fan control , ltc and lt are registered trademarks of linear technology corporation. i 2 c is a trademark of philips electronics n.v.
ltc1840 2 top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 scl sda a1 a0 fault gpio1 gpio2 gnd v cc i dacouta i dacoutb blast tachb tacha gpio4 gpio3 v cc to gnd .................................................... C0.5 to 6v a0, a1 ............................................. C0.3 to (v cc + 0.3v) i dacouta , i dacoutb ............................. C0.3 to (v cc + 0.75v) all other pins ................................................. C0.3 to 6v operating temperature ltc1840c ............................................... 0 c to 70 c ltc1840i .............................................C40 c to 85 c storage temperature range ..................C65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number gn part marking t jmax = 125 c, q ja = 110 c/w consult ltc marketing for parts specified with wider operating temperature ranges. 1840 1840i ltc1840cgn ltc1840ign absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 3v symbol parameter conditions min typ max units dacs n resolution 8 bits dnl differential nonlinearity v dacout = 1.1v, guaranteed monotonic l 0.9 lsb inl integral nonlinearity v dacout = 1.1v 4lsb zse zero-scale error v dacout = 1.1v C0.2 0.1 2 m a output voltage rejection 1.1v< v dacout < 3.75v 1lsb output voltage rejection v cc = 5.75v, 1.1v < v dacout < 6.5v 2lsb i dacouta(fs), full-scale current sinking 97 103 m a i dacoutb(fs) l 95 105 m a power supply v cc positive supply voltage l 2.7 5.75 v i cc supply current v cc = 3v 400 m a v cc = 5v 500 m a v uvlo uvlo/por voltage l 2.1 2.4 2.69 v v uvhys uvlo/por voltage hysteresis (note 2) 20 90 160 mv oscillator performance f osc oscillator frequency l 47 50 53 khz psrr supply sensitivity 2.7v < v cc < 5.75v 0.1 0.5 %/v gpio performance i o output current sink v gpiox = 0.7v, internal pull-down enabled l 10 ma v il digital input low voltage internal pull-down disabled l 0.3v cc v v ih digital input high voltage internal pull-down disabled l 0.7v cc v v ihyst input hysteresis (note 2) 50 mv i leak leakage internal pull-down disabled 1 m a
ltc1840 3 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 3v note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: guaranteed by design not subject to test. symbol parameter conditions min typ max units digital inputs scl, sda v ih digital input high voltage l 1.4 v v il digital input low voltage l 0.6 v v lth logic threshold voltage (note 2) 1 v i leak digital input leakage v cc = 5v and 0v, v in = gnd to v cc 1 m a c in digital input capacitance (note 2) 10 pf digital output sda v ol digital output low voltage i pull-up = 3ma l 0.4 v digital output fault v ol digital output low voltage i pull-up = 1ma l 0.4 v digital inputs tacha, tachb v ih digital input high voltage l 0.7v cc v v il digital input low voltage l 0.3v cc v i leak digital input leakage v cc = 5v and 0v, v in = gnd to v cc 1 m a digital input blast v lth logic threshold voltage measured on blast falling edge 0.95 1.0 1.05 v v ihyst input hysteresis (note 2), measured on rising edge 20 mv i leak digital input leakage v cc = 5v and 0v, v in = gnd to v cc 1 m a address inputs a0, a1 v ih input high voltage l 0.9v cc v v il input low voltage l 0.1v cc v i in input current ax shorted to gnd or v cc , v cc = 5v 100 m a timing characteristics f i2c i 2 c operating frequency (note 2) 0 100 khz t buf bus free time between (note 2) 4.7 m s stop and start condition t hd, sta hold time after (repeated) (note 2) 4 m s start condition t su, sta repeated start condition (note 2) 4.7 m s setup time t su, sto stop condition setup time (note 2) 4 m s t hd, dat data hold time 300 ns t su, dat data setup time (note 2) 250 ns t low clock low period (note 2) 4.7 m s t high clock high period (note 2) 4.0 m s t f clock, data fall time (note 2) 300 ns t r clock, data rise time (note 2) 1000 ns
ltc1840 4 uu u pi fu ctio s scl (pin 1): serial clock input. the 2-wire bus master device clocks this pin at a frequency between 0khz and 100khz to enable serial bus communications. data at the sda pin is shifted in or out on rising scl edges. scl has a logic threshold of 1v and an external pull-up resistor or current source is normally required. sda (pin 2): serial data input. this is a bidirectional data pin which normally has an external pull-up resistor or current source and can be pulled down by the open drain device on the ltc1840 or by external devices. the master controls sda during addressing, the writing of data, and read acknowledgment, while the ltc1840 controls sda when data is being read back and during write acknowl- edgment. sda data is shifted in or out on rising scl edges. sda has a logic threshold of 1v. a1 (pin 3): three state address programming input. this pin can cause three different logic states internally, de- pending upon whether it is pulled to supply, pulled to ground, or not connected (nc). combined with the a0 pin, this provides for nine different possible two-wire bus addresses for the ltc1840 (see table 1). a0 (pin 4): three state address programming input. see a1. fault (pin 5): fault indicator pull-down output. this pin has an open drain pull-down that is used to signal various fault conditions on the ltc1840. an external 10k pull-up is recommended. gpio1, gpio2, gpio3, gpio4 (pins 6, 7, 9, 10): general purpose inputs/outputs. these pins can be used as digital inputs with cmos logic thresholds or digital outputs/led drivers with open drain pull-downs that can be pro- grammed to blink. gpio pins can be programmed to produce faults due to changes in their logic states, and these faults can only be cleared by software or powering the ltc1840 down. all gpios default to nonfaulting logic inputs upon power-up and their functionality is changed through the serial interface. gnd (pin 8): ground. connect to analog ground plane. tacha (pin 11): tachometer input a. this pin is a digital input that is designed to interface to the tachometer output from a 3-wire fan. internal logic will count between rising tacha edges at serially programmable frequencies of 25khz, 12.5khz, 6.25khz or 3.125khz and the most re- cently completed count is stored in a register accessible through the serial interface. the maximum count is 255 and the ltc1840 is programmable to produce faults when block diagra w 8-bit idacs gpi/o interface 8-bit counter 8-bit counter fault detect ref osc ? 2, 4, 8, 16 15 1 2 3 4 14 5 13 10 11 12 9 7 6 i dacouta i dacoutb fault blast gpio1 gpio2 gpio3 gpio4 tachb tacha scl sda a1 a0 serial interface 1840 bd 8 gnd ii
ltc1840 5 t low t high t su, dat t su, sto t su, sta t buf t hd, sta t hd, dat t hd, sta t r t f start condition stop condition repeated start condition start condition 1840 td01 sda scl ti i g diagra u ww a count exceeds this number. this pin has cmos thresh- olds and the default conditions are to count at 3.125khz and to not produce faults. tachb (pin 12): tachometer input b. see tacha blast (pin 13): blast/timer function input. this is a multifunction digital input pin that controls blast and timer operation. if this pin is in a logic high state at power-up or is transitioned from high to low, it will blast the current dac outputs to full scale (100 m a) no matter what their previous state was and set a fault condition. in addition, if blast is in a logic high state, the serial access timer is active; this circuit measures time between serial commu- nications to the ltc1840 and forces a blast and trips a fault if the part hasnt been accessed for about 1.5 minutes. this pin has a 1v logic threshold. typical 2-wire serial i 2 c or smbus transmission stop condition 8 1-7 9 8 1-7 9 8 1-7 9 s p start condition address ack ack ack r/w data data sda scl 1840 td02 uu u pi fu ctio s i dacoutb (pin 14): current dac output b. this is a high impedance output with a maximum sinking current output of 100 m a. this current can be programmed to one of 256 values through the serial interface or it can be blasted immediately to full scale using the blast pin or by the serial access timer if it is enabled and the ltc1840 is not accessed for about 1.5 minutes. this pin will maintain the programmed current to a very tight tolerance from as low as 1.1v to at least 0.75v above v cc . the current dac is guaranteed to be monotonic over its full 8-bit range. i dacouta (pin 15): current dac output a. see i dacoutb v cc (pin 16): positive supply. this pin must be closely decoupled to ground (pin 8). a 10 m f tantalum and a 0.1 m f ceramic capacitor in parallel are recommended. operatio u
ltc1840 6 serial interface simple 2-wire interface multiple devices on same bus idle bus must have sda and scl lines high ltc1840 is read/write master controls bus devices listen for unique address that precedes data the start and stop conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (low active) generated by the slave lets the master know that the latest byte of information was received. the acknowledge- related clock pulse is generated by the master. the trans- mitter master releases the sda line (high) during the acknowledge clock pulse. the slave receiver must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. when a slave receiver doesnt acknowledge the slave address (for example, its unable to receive because its performing some real-time function), the data line must be left high by the slave. the master can then generate a stop condition to abort the transfer. if a slave receiver acknowledges the slave address, but some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. this is indicated by the slave generating the not acknowledge on the first byte to follow. the slave leaves the data line high and the master generates the stop condition. commands supported the ltc1840 supports read byte, write byte, read word (the second data byte will be all ones) and write word (the second data byte will be ignored) commands. data transfer timing for write commands in order to help assure that bad data is not written into the ltc1840, data from a write command is only stored after a valid acknowledge has been performed. the part will detect that sda is low on the rising edge of scl that marks the end of the period in which the ltc1840 acknowledges the data write and then latch the data during the following scl low period. operatio u start 1 1 1 b4 b3 b2 b1 x x x x x r2 r1 r0 wr ack ack d7 d6 d5 d4 d3 d2 d1 d0 ack stop slave address register address s 0 s 0 s 0 0 data byte 1 11 111 7 88 start 1 1 1 b4 b3 b2 b1 x x x x x r2 r1 r0 wr ack ack d7 d6 d5 d4 d3 d2 d1 d0 ack stop slave address register address s 0 s 0 m 1 0 data byte 111 1 ack s 0 111 7 start 1 1 1 b4 b3 b2 b1 rd slave address 1 11 7 8 8 1840 td03 ltc1840 write byte protocol ltc1840 read byte protocol
ltc1840 7 ltc1840 device addressing it is possible to configure the part to operate with any one of nine separate addresses through the three state a0 and a1 pins. table 1 shows the correspondence of addresses to the states of the pins: table 1. device addressing ltc1840 device address 2-wire bus slave address bits a0 a1 b4 b3 b2 b1 lnc0000 nch0001 ncnc0010 hnc0011 ll0100 hh0101 ncl0110 hl0111 lh1000 for the a0 and a1 lines, l refers to a grounded pin, h is a pin shorted to v cc and nc is no connect. the pin voltage will be set to approximately v cc /2 when not connected. bits b7, b6 and b5 of the address are hardwired to 111. register addresses and contents fault conditions are cleared by the action of writing to the fault register, but the data byte from the write command is not actually loaded into the register. a tacha/b flt bit will be high if the corresponding tacha/b flten bit in the status register has been set high and the corresponding tacha/b counter has overflowed its maximum count of 255. these faults are latched internally and must be cleared by writing to the fault register. the fault will be reasserted if the counter is still in overflow after a write to the fault register. the tach flt bits power-up in the low state. the blast and timer bits become high after blasting and serial access time-out events, respectively. a high gpiox flt bit reflects that the gpiox pin has caused a fault condition; to do so, the pin must be enabled as fault producing in the gpio setup register (gpiox flten set high) and the logic state of the pin must change after the enable. the fault is latched internally and must be cleared through software, by writing to the fault register; a change in the state of the gpiox pin from its state at the point of the fault register being written will cause another fault to be signalled. operatio u register register name address data byte (r/w) r2 r1 r0 d7 d6 d5 d4 d3 d2 d1 d0 fault 000 tacha flt tachb flt blast timer gpi04 flt gpi03 flt gpi02 flt gpi01 flt (0) (0) (0) (0) (0) (0) (0) (0) status 001 tacha flten tachb flten div1 div0 *see note 2 (0) (0) (0) (0) (0/1) (0) (0) (1) daca 010 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb (0) (0) (0) (0) (0) (0) (0) (0) dacb 011 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb (0) (0) (0) (0) (0) (0) (0) (0) tacha 100 cnt a7 cnt a6 cnt a5 cnt a4 cnt a3 cnt a2 cnt a1 cnt a0 (1) (1) (1) (1) (1) (1) (1) (1) tachb 101 cnt b7 cnt b6 cnt b5 cnt b4 cnt b3 cnt b2 cnt b1 cnt b0 (1) (1) (1) (1) (1) (1) (1) (1) gpio data 110 gpio4 pin gpio3 pin gpio2 pin gpio1 pin gpio4 reg gpio3 reg gpio2 reg gpio1 reg (n/a) (n/a) (n/a) (n/a) (1) (1) (1) (1) gpio setup 111 gpio4 blnk gpio3 blnk gpio2 blnk gpio1 blnk gpio4 flten gpio3 flten gpio2 flten gpio1 flten (0) (0) (0) (0) (0) (0) (0) (0) table 2. ltc1840 register address and contents note 1: number in ( )signifies default bit status upon power-up. note 2: state of bit depends on slave address used.
ltc1840 8 div1 and div0 program the ratio by which the oscillator frequency is divided down to produce the tachometer clocks (2, 4, 8, or 16). the div bits power-up low, which corresponds to a frequency division of 16. for example, if div1 and div0 are both high, the divide ratio is set to 2. if div1 is high and div0 is low, the divide ratio is set to 4. if div1 is low and div0 is high, the divide ratio is set to 8. the tacha and tachb registers will be set to all ones by a uvlo condition. the tach counters count between rising edges on the tacha and tachb pins. if a counter overflows its maximum count of 255, the latch holding the count results is immediately set to 255 without waiting for the next edge on its tach pin. this is done so that a suddenly stopped or locked rotor will be easily detectable by reading its corresponding tach register; otherwise, the register would merely hold the previous count and be waiting for a tach signal edge that isnt coming to update the overflow count. the gpiox pin bits in the gpio data register reflect the logic state of the pin itself, while the gpiox register bits reflect the data that is stored in the register that controls the gate of the internal pull-down for the pin. the logic polarities of the gpiox bits are the same as those of the gpiox pins assuming an appropriately sized pull-up resis- tor (for example, a 1 value for the gpio1 register bit will force the internal n-channel mosfet pull-down to an off- state, resulting in a 1 value at the gpio1 pin). for a gpio to be used as a digital input, the gpiox register bit is set high, which turns off the internal pull-down n-channel mosfet, and the state of the pin can be controlled externally and read back via the gpiox pin bit. the gpio register bits power-up in the high state. the gpiox blnk bits in the gpio setup register control whether the internal pull-down on a gpio shuts on and off at about 1.5hz when the gpiox register bit is low, and the gpiox flten bits control whether a gpio pin can trigger a fault condition by a change in state. the gpio flten and gpio blnk bits power-up in the low state. serial interface example in this example, an ltc1840 has both address pins open (nc) and the output current of daca will be programmed to half of full-scale (50 m a). provide a start condition on the bus by pulling sda from high to low while scl is high and then write the sda bit stream 1110010 to the part for the ltc1840 slave address, followed by a 0 to indicate that a write operation will follow. all sda transitions must happen when scl is low, or a start or stop condition will be interpreted. the ltc1840 will then pull the sda line low during the next scl clock phase to indicate that it is responding to the communication attempt. to write to the daca output register, write 00000010 to the ltc1840 and wait for the ltc1840 to acknowledge again on the following scl cycle by pulling sda low. next, send the ltc1840 the value indicating the daca current; writing the sda data stream 10000000 sets the dac to sink 50 m a. the ltc1840 will then acknowledge a third time by pulling sda low for the next scl cycle. then the data will be written into the internal daca register and i dacouta pin will sink 50 m a. now generate a stop condition by forcing sda from low to high while scl is high. tachometer interface operation it is common for fans to have tachometer outputs that produce two pulses per blade revolution. the ltc1840 provides two inputs that interface to circuits that count between rising edges on these pulses. the frequency at which the counting is done is programmable via the serial interface to 25khz, 12.5khz, 6.25khz, and 3.125khz, equivalent to divide by 2, 4, 8, and 16 operations from a 50khz oscillator. the count values corresponding to these two inputs can also be read via the serial interface. the output registers storing these counts power-up to all ones, and they will also be loaded with all ones whenever a counter overflows between two rising edges to allow for the detection of a suddenly stopped rotor. the part can also be configured to produce a fault as soon as the counter overflows. however, the default state is to not produce such faults, so as to prevent unnecessary fault conditions while the fan is spinning up at start-up. operatio u
ltc1840 9 multiple fans with open drain tachometer output signals can be connected to a single ltc1840 tachometer input in a wired-or fashion, as long as the fans are not active at the same time. if the fans happen to be spinning simulta- neously, the counts in the tach registers will not be meaningful. gpio operation the gpio circuits feature n-channel mosfet open drain pull-downs that can drive leds and readback circuitry to allow the logic states of the gpio pins to be accessed through the serial interface. the circuits that read the logic states of the pins have standard cmos thresholds. the user must take care to minimize the power dissipation in the pull-downs. leds should have series resistors added to limit current and to limit the voltage drop across the internal pull-down if their forward drop is less than about v cc minus 0.7v. the n-channel mosfet pull-downs can sink 10ma at 0.7v drop to drive leds. a series resistor is usually required to limit led current and the ltc1840 internal power dissipation. see table 3 for resistor values. table 3. recommended led resistor values recommended led current (ma) series resistor ( w ) v cc = 3v v cc = 5v 11k3k 3 270 910 5 120 510 10 30 240 note: led forward voltage drop assumed to be 2v. fault operation normally, the fault pin internal pull-down is only en- abled if one of the fault bits in the fault register is high. but it is also enabled if the part is shut down by the por block due to low v cc supply. this por fault does not have a corresponding fault register bit. blast and timer operation the blast pin is used to force the dac output currents to full value instantaneously and also to gate the operation of the serial interface timer. a blast will occur if the blast pin is high when the part comes out of por or if there is a high to low transition on blast after por. the threshold of the blast pin is about 1v, independent of v cc . the serial access timer, which will signal a fault condition if the part has not been addressed via the serial interface for about a minute and a half, is only active if the blast pin is high. if neither blasts nor an active serial access timer are desired, this pin should be tied to ground. if timer opera- tion is desired without having a blast occur at power-up, the pin should be pulled above 1v after the parts supply has ramped up. the blast state is cleared by writing to the fault register. current output dac interface to switching regulator the output of a current dac is used to control the output voltage of a switching regulator that powers a fan, which determines the rotational speed of the fan. the resistor divider from the output of the regulator to the feedback pin to ground should be ratioed to give the minimum desired voltage from the fan, which corresponds to the minimum fan speed. the size of the resistor from the output to the feedback pin is then chosen by dividing the difference between the maximum and minimum desired fan voltages by the nominal maximum current output of the dac, which is 100 m a. the value of the resistor from the feedback pin to ground is then derived from the divider ratio and the resistor value just calculated. for example, if the feedback pin of the regulator is at 1.25v with respect to ground and the minimum desired fan voltage is 5v, the top resistor in the divider should be (5v C 1.25v)/1.25v = 3 times larger than the resistor from the feedback node to ground. if the maximum desired fan voltage is 12v, the top resistor value is then (12v C 5v)/ 100 m a = 69.8k, and the bottom resistor is 69.8k/3 = 23.2k. see figure 1. operatio u
ltc1840 10 if the feedback pin voltage of a regulator is lower than the 1.1v compliance voltage of either of the ltc1840s cur- rent output dacs, the resistor from the regulator output to the feedback pin can be divided into two resistors, giving the dac more room to operate. see figure 2. if more than one fan is controlled by one regulator output, small differences in the actual rotational speeds of the fans operatio u figure 1. feedback divider for 1.25v reference figure 3. series diode to avoid beat frequencies figure 2. feedback divider for 0.8v reference v out (5v to 12v) r1 69.8k r2 23.2k v fb 1.25v i dac regulator fb 15(14) i dacouta (i dacoutb ) ltc1840* 1840 f01 *additional details omitted for clarity v out (5v to 12v) r3 69.8k r1 10k r2 15k v fb 0.8v 1.3v i dac regulator fb 15(14) i dacouta (i dacoutb ) ltc1840* 1840 f02 *additional details omitted for clarity v out bys10-25 fan 1 fan 2 fan 1, fan 2: nmb 6820pl-04w-b49-d50 1840 f03 may result in audible beat frequencies, which can be very annoying. to avoid this problem, the actual voltages applied to the fans can be varied by adding resistors or diodes in series with some of the fans, resulting in larger differences between their rotational speeds and less noticeable beating. see figure 3.
ltc1840 11 gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.009 (0.229) ref package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
ltc1840 12 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 2001 1840i lt/tp 0601 1.5k ? printed in usa related parts typical applicatio u part number description comments ltc1625 no r sense tm current mode synchronous step-down up to 97% efficiency; up to 3mhz operation; switching regulator no external diode; 0.85v start-up voltage ltc1695 smbus/i 2 c fan speed controller in thinsot tm 0.75 w pmos linear regulator with 180ma output current rating ltc1694/ltc1694-1 smbus accelerator includes dc and ac pull-up current/ac pull-up current only ltc1771 ultralow suply current step-down dc/dc controller 10 m a supply current; 93% efficiency; 1.23v v out 18v; 2.8v v in 20v ltc4300-1 hot swappable 2-wire bus buffer prevents sda, scl corruption during live insertion; bidirectional bus buffer; isolates backplane and card capacitance no r sense and thinsot are trademarks of linear technology corporation. 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 ltc1840 1 2 3 4 5 6 7 8 extv cc sync run/ss fcb i th sgnd v osense v prog v in tk sw tg b00st intv cc bg pgnd 1 2 3 4 5 6 7 8 10k 10k 130 led1 nc nc to automatically mux tacha between the two parallel fans, set gpio2 to blink address = 1110010 (8 others possible) l1 = sumida cdrh125-15omc c in , c out , = panasonic eev-fc1c471p r1, r2 = 1% metal film ltc1625 + + + c in1 470 f c in2 470 f 4.7k + cc1 470pf cf1 100pf cc2 220pf cb, 0.22 f 10k cv cc 4.6 f cv in 0.1 f si4410dy si4410dy l1 15 h mbrs140t3 + r1 75k r2 27k c out1 470 f 2 3.3v 3.3v 3.3v 3.3v scl sda a1 a0 fault gpio1 gpio2 gnd v cc i dacouta i dacoutb blast tachb tacha gpio4 gpio3 dc fan dc fan 1840 ta03 cmdsh-3 system reset ltc1840 tach out tach out bys10-25 extv cc sync run/ss fcb i th sgnd v osense v prog v in tk sw tg b00st intv cc bg pgnd 1 2 3 4 5 6 7 8 ltc1625 + + c in1b 470 f c in2b 470 f 4.7k + cc1b 470pf cf1b 100pf cc2b 220pf cbb, 0.22 f 10k cv ccb 4.6 f cv inb 0.1 f si4410dy si4410dy l1b 15 h mbrs140t3 + r1b 75k r2b 27k i_39 470 f 2 dc fan dc fan cmdsh-3 tach out tach out 10k 10k 10k in4148 10k 12v 2- nmb 5910pl-04w-b59-d50 fans 2.1a nom at 12v 2- nmb 5920pl-04w-b29-d50 fans 2.2a nom at 12v (4.5v to 12v) (4.5v to 12v) tp0101ts tn0205a sda scl fault -a- -a- 0.1 f 10 f controlling fan pair with automatic blast redundancy and fan pair with automatic tach muxing

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